Store→Load Reordering: x86 vs ARM64 Real-World Test

Same C code, two architectures, two different observable behaviors. x86-64’s TSO model hides store→load reordering most of the time; ARM64’s weaker model lets you see it directly. This video runs a minimal test that demonstrates the difference and prints the reorder count.

If you’ve written lock-free code that “worked on x86 but broke on ARM,” this is the underlying mechanism.

What the test shows

• In the video: five runs per CPU. On the x86-64 Intel machine, one to five reorders appeared per half a million iterations. On ARM64, most runs showed about five to ten, with one run reaching 30. With a memory fence, both architectures showed none.
• In the blog post’s ARM64 run over a million iterations, the both-zero outcome appeared ~2.3% of the time with no barrier, ~1.8% with only a compiler barrier, and 0.0% with a dsb sy fence. A compiler barrier alone does not fix it; you need a real CPU fence.

Related

• Blog post: store→load reordering — x86 vs ARM64 and what fences do